The present invention relates to a semiconductor device and relates to, for example, a semiconductor device that includes an operational amplifier.
An input offset, which is a difference between a threshold voltage of an inverting input terminal and a threshold voltage of a non-inverting input terminal due to variations or the like of semiconductor elements during a manufacturing process, occurs in an operational amplifier. It is required to minimize this input offset since the input offset causes an error in results of amplification when minute signals are amplified. However, a modification of only the manufacturing process is not enough to reduce the input offset. Japanese Unexamined Patent Application Publication No. 2006-311350 discloses a method of correcting the input offset.
The configuration disclosed in Japanese Unexamined Patent Application Publication No. 2006-311350 includes an operational amplifier that includes an offset adjustment input terminal, a first switching element for short-circuiting a non-inverting input terminal and an inverting input terminal of the operational amplifier, a second switching element for disconnecting the inverting input terminal of the operational amplifier from a negative-phase input signal, one or more latch circuits that regard an output voltage of the operational amplifier as a binary logical signal formed of a logical value quantized by a weighted offset adjustment amount and latch the output voltage, a storage circuit that stores the logical signal that has been latched by the latch circuit(s), and a control circuit that generates an offset adjustment signal of the operational amplifier in accordance with the logical signal stored in the storage circuit and outputs the offset adjustment signal to the offset adjustment input terminal, whereby the offset of the output voltage is corrected.